1. Field of the Invention
The present invention relates to an integrated circuit and an electric device using thereof. More particularly, it relates to improvement of techniques when the integrated circuit comprises a plurality of processors and the plurality of processors access a shared memory via a bus.
2. Description of the Related Art
In recent years, multimedia data composed of video data, audio data and other kinds of data, is often processed in an electric device. In the electric device, a special-purpose processor or a general-purpose processor, mounted therein, processes the multimedia data.
When the processor mounted therein has very high performance and power consumed by the processor need not be saved, all of necessary processes can be performed by the processor alone.
However, a portable electric device, e.g., a cellular phone, a PDA, a digital video camera, a digital still camera, and so on, is powered by a battery in most cases. Therefore, in the portable electric device, it is desirable to reconcile reducing power consumption and improving performance so that the portable electric device becomes smaller, lighter and more efficient. There is the same problem as described above, in a non-portable electric device, e.g. a DVD player, a DVD recorder, HD recorder, and so on, for saving resources and/or energy.
A document (title: “System LSI techniques for MPEG-4 LSI”, TOSHIBA REVIEW, Vol. 57, No. 1 (2002)) discloses the following points, to reconcile retaining sufficient performance and reducing power consumption in an integrated circuit, which processes the multimedia data.
(Point 1) Since it is difficult to acquire sufficient throughput only by a single processor, a processor that processes video signals and a processor that processes audio signals are provided, that is, a multi-processor configuration is adopted.
(Point 2) Considering that I/O between chips of a processor consumes more than one half of the power, a memory, which is shared by both the processor that processes the video signals and the processor that processes the audio signals, is provided in an integrated circuit of the processor, and these processors access the shared memory via a bus. Thereby, reducing the power consumed by the I/O between the chips.
Next, referring to FIG. 2, the conventional technique will now be explained more concretely. FIG. 2 is an outline block diagram of a conventional integrated circuit.
As shown in FIG. 2, an integrated circuit 1 comprises a bus 2 in itself. A shared memory 3 is connected to the bus 2.
A video processor 4 processing video signals, an audio processor 5 processing audio signals, and a multiplex/de-multiplex processor 6 multiplexing/de-multiplexing a bit stream, are provided, that is, a multi-processor configuration is adopted. These processors 4, 5 and 6 are connected to the bus 2. Herein, the video processor 4, the audio processor 5 and the multiplex/de-multiplex processor 6 have buffer memories 7, 8 and 9 in themselves, respectively.
These processors 4, 5, and 6 access the shared memory 3 via the bus 2 and perform processes in parallel, cooperating with each other.
According to this configuration, since the shared memory 3 is accessed from all of the video processor 4, the audio processor 5, and the multiplex/de-multiplex processor 6, access to the bus 2 may be contended. Then, the bus 2 arbitrates the access. As a result, since at least one of the processors 4, 5 and 6 should await access, latency time must arise.
Processes of the video processor 4 are heavier than those of the audio processor 5 and the multiplex/de-multiplex processor 6. Unless the video processor 4 accesses the shared memory 3 at high speed without latency time, the processes of the video processor 4 delay and the video processor 4 may not be able to complete processes to be done in a predetermined time.
Since the conventional techniques fail to consider that load of one of the plurality of processors is different from those of the other, in some cases, the plurality of processors as a whole cannot complete processes to be done in real time.